In the above-mentioned context, where two modules write/read in the same memory workspace, two separate techniques are currently known.
A first known technique consists in utilizing a DPRAM memory. This first known technique is practically necessary when the first and second modules are, respectively, a very fast processing unit (CPU) and a very fast controller (IP block), such as a USB controller, for example. In these cases, the CPU accesses and the controller accesses (e.g., USB) are served concurrently, without waiting.
A second known technique consists in utilizing an SRAM memory with a “cycle-stealing” mechanism (also called a wait mechanism). This second known technique is more suited to the case where the first and second modules are, respectively, a processing unit (CPU) and a slower controller (IP block), such as a CAN controller, for example. When concurrent accesses are detected, the wait mechanism is implemented (sending of a “wait” signal by the SRAM memory or by an arbitration device placed between the SRAM memory and the first and second modules), in order to make either the CPU or the controller wait during the entire duration of a clock cycle of the SRAM memory. Conventionally, the clock of the SRAM memory is expressed either in the time base of the first module (e.g., the CPU), or in that of the second module (e.g., a controller). In other words, the clock signal received at the input of the SRAM memory comes from the first or from the second module.
The aforesaid two known techniques have advantages and disadvantages.
The DPRAM are admittedly very efficient, because there are no conflicts in the event of concurrent access. Their major disadvantage is size (nearly twice that of an SRAM memory with an equivalent capacity) and, above all, heavy technological dependency. It is still actually possible to find technologies that do not propose DPRAM.
The advantage of the SRAM is their smaller size in relation to the DPRAM and, above all, there is definitely not any technological dependency. Their disadvantage is the fact that they impose a wait time either on the CPU or the controller, in order that concurrent accesses might be served. Moreover, if a wait mechanism has not been anticipated, the frequency must be doubled in order to be able to serve two requests, with consequences affecting the system's consumption.
It is pointed out that, in an alternative to the second technique, the memory workspace is produced in the form of a register instead of an SRAM memory. The advantages and disadvantages of this alternative are substantially the same as those of the second known technique (with SRAM memory).